VXI Extensions for C-size

The VXIbus specification for C-size includes a number of important extensions for data acquisition and ATE applications. These include:

• 10 MHz ECL System Clock PM100ppm.
• 8 TTL chassis-wide trigger lines.
• 2 ECL chassis-wide trigger lines.
• Analog SUMBUS 50OMEGA summing node, current source driven.
• 12-line Local Bus propagated from slot to slot.

10 MHz ECL System Clock
Trigger Lines
Analog SUMBUS
Local Bus

10 MHz ECL System Clock

The Slot-0 Controller is responsible for generating the 10 MHz system clock. Good module design practice derives timing from this clock so that all data sampling elements within a mainframe remain in lock step.

Trigger Lines

The specification provides for 2 ECL and 8 TTL trigger lines that are available at each slot in the backplane. These lines are particularly useful for distributing clock and timing information on a chassis-wide basis. The TTL trigger lines are open collector and both the TTL and ECL trigger lines can be driven by any module in the mainframe. Three trigger line protocols are defined by the specification:

SYNC

The synchronous protocol is the most commonly used. Any module can assert the trigger and one or more modules may monitor the line.

ASYNC

The asynchronous protocol involves two trigger lines with a single source and single acceptor. The source initiates action by pulling the lower numbered line and the acceptor acknowledges by asserting the higher numbered line.

Start/Stop

In this mode the Slot-0 drives the line and one state signifies start and the other stop.

Bustec modules make extensive use of the trigger lines and use a very flexible trigger matrix switch for allocating trigger lines for various module and chassis-wide functions.

Analog SUMBUS

The Analog SUMBUS is a 50OMEGA terminated bus. Modules may drive the bus with a current source as well as monitor the sum of the currents into the 50OMEGA load.

Local Bus

The Local Bus is a 12-line bus that is propagated from slot to slot by each module in the chain. The backplane connects LBUS-row-C pins of slot N to LBUS-row-A pins of slot N+1. A module designer chooses which set of pins to receive or send data and whether data is propagated through the module. This feature provides a convenient way of providing a private communications path between modules that form a group.

A wide range of signaling is allowed on the Local Bus by the VXIbus specification. Although not foolproof, the specification provides for keying of modules that use local bus. The objective is to minimize the chance of inserting modules that use incompatible signaling techniques in adjacent slots. Six classes are defined TTL, ECL, Analog low, medium, and high. One class is reserved.